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<div class="title">xaxidma_hw.h File Reference</div>  </div>
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
Macros</h2></td></tr>
<tr><td colspan="2"><div class="groupHeader">DMA Transfer Direction</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Buffer Descriptor Alignment</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Micro DMA Buffer Address Alignment</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Maximum transfer length</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This is determined by hardware </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Device registers</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Register sets on TX and RX channels are identical </p>
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<tr class="memitem:ga79d2eca90f2554b8c893b2f9a70c795c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga79d2eca90f2554b8c893b2f9a70c795c">XAXIDMA_RX_CDESC0_OFFSET</a>&#160;&#160;&#160;0x00000040</td></tr>
<tr class="separator:ga79d2eca90f2554b8c893b2f9a70c795c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Bitmasks of XAXIDMA_CR_OFFSET register</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Bitmasks of XAXIDMA_SR_OFFSET register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register reports status of a DMA channel, including run/stop/idle state, errors, and interrupts (note that interrupt masks are shared with XAXIDMA_CR_OFFSET register, and are defined in the _IRQ_ section.</p>
<p>The interrupt coalescing threshold value and delay counter value are also shared with XAXIDMA_CR_OFFSET register, and are defined in a later section. </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Bitmask for interrupts</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>These masks are shared by XAXIDMA_CR_OFFSET register and XAXIDMA_SR_OFFSET register </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Bitmask and shift for delay and coalesce</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>These masks are shared by XAXIDMA_CR_OFFSET register and XAXIDMA_SR_OFFSET register </p>
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<tr><td colspan="2"><div class="groupHeader">Buffer Descriptor offsets</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>USR* fields are defined by higher level IP.</p>
<p>setup for EMAC type devices. The first 13 words are used by hardware. All words after the 13rd word are for software use only. </p>
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<tr><td colspan="2"><div class="groupHeader">Bitmasks of XAXIDMA_BD_CTRL_OFFSET register</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Bitmasks of XAXIDMA_BD_STS_OFFSET register</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Bitmasks and shift values for XAXIDMA_BD_MCCTL_OFFSET register</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Bitmasks and shift values for XAXIDMA_BD_STRIDE_VSIZE_OFFSET register</div></td></tr>
<tr class="memitem:ga99f615c527035db697545614fff86bf2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga99f615c527035db697545614fff86bf2">XAxiDma_ReadReg</a>(BaseAddress,  RegOffset)                      &#160;&#160;&#160;XAxiDma_In32((BaseAddress) + (RegOffset))</td></tr>
<tr class="separator:ga99f615c527035db697545614fff86bf2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga96d7b2834ae100f53627ca961393e9a2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga96d7b2834ae100f53627ca961393e9a2">XAxiDma_WriteReg</a>(BaseAddress,  RegOffset,  Data)                &#160;&#160;&#160;XAxiDma_Out32((BaseAddress) + (RegOffset), (Data))</td></tr>
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